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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ISR_EL1, Interrupt Status Register</h1><p>The ISR_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Shows the pending status of the IRQ, FIQ, or SError interrupt.</p>

      
        <p>When executing at EL2, EL3 or Secure EL1 when <a href="AArch64-scr_el3.html">SCR_EL3</a>.EEL2 == <span class="binarynumber">0b0</span>, this shows the pending status of the physical IRQ, FIQ, or SError interrupts.</p>

      
        <p>When executing at either Non-secure EL1 or at Secure EL1 when <a href="AArch64-scr_el3.html">SCR_EL3</a>.EEL2 == <span class="binarynumber">0b1</span>:</p>

      
        <ul>
<li>If the <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{IMO,FMO,AMO} bit has a value of 1, the corresponding ISR_EL1.{I,F,A} bit shows the pending status of the virtual IRQ, FIQ, or SError.
</li><li>If the <a href="AArch64-hcr_el2.html">HCR_EL2</a>.{IMO,FMO,AMO} bit has a value of 0, the corresponding ISR_EL1.{I,F,A} bit shows the pending status of the physical IRQ, FIQ, or SError.
</li></ul>
      <h2>Configuration</h2><p>AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-isr.html">ISR[31:0]</a>.</p><h2>Attributes</h2>
        <p>ISR_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_11">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="21"><a href="#fieldset_0-63_11">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10-1">IS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9-1">FS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">A</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">I</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6">F</a></td><td class="lr" colspan="6"><a href="#fieldset_0-5_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_11">Bits [63:11]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_10-1">IS, bit [10]<span class="condition"><br/>When FEAT_NMI is implemented:
                        </span></h4><div class="field">
      <p>IRQ with Superpriority pending bit. Indicates whether an IRQ interrupt with Superpriority is pending.</p>
    <table class="valuetable"><tr><th>IS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No pending IRQ with Superpriority.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An IRQ interrupt with Superpriority is pending.</p>
        </td></tr></table></div><h4 id="fieldset_0-10_10-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9-1">FS, bit [9]<span class="condition"><br/>When FEAT_NMI is implemented:
                        </span></h4><div class="field">
      <p>FIQ with Superpriority pending bit. Indicates whether an FIQ interrupt with Superpriority is pending.</p>
    <table class="valuetable"><tr><th>FS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No pending FIQ with Superpriority.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An FIQ interrupt with Superpriority is pending.</p>
        </td></tr></table></div><h4 id="fieldset_0-9_9-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8">A, bit [8]</h4><div class="field">
      <p>SError interrupt pending bit. Indicates whether an SError interrupt is pending.</p>
    <table class="valuetable"><tr><th>A</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No pending SError.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An SError interrupt is pending.</p>
        </td></tr></table>
      <p>If the SError interrupt is edge-triggered, this field is cleared to zero when the physical SError interrupt is taken.</p>
    </div><h4 id="fieldset_0-7_7">I, bit [7]</h4><div class="field">
      <p>IRQ pending bit. Indicates whether an IRQ interrupt is pending.</p>
    <table class="valuetable"><tr><th>I</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No pending IRQ.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An IRQ interrupt is pending.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This bit indicates the presence of a pending IRQ interrupt regardless of whether the interrupt has Superpriority.</p>
      </div>
    </div><h4 id="fieldset_0-6_6">F, bit [6]</h4><div class="field">
      <p>FIQ pending bit. Indicates whether an FIQ interrupt is pending.</p>
    <table class="valuetable"><tr><th>F</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No pending FIQ.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>An FIQ interrupt is pending.</p>
        </td></tr></table>
      <div class="note"><span class="note-header">Note</span>
        <p>This bit indicates the presence of a pending FIQ interrupt regardless of whether the interrupt has Superpriority.</p>
      </div>
    </div><h4 id="fieldset_0-5_0">Bits [5:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing ISR_EL1</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, ISR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1100</td><td>0b0001</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGRTR_EL2.ISR_EL1 == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        X[t, 64] = ISR_EL1;
elsif PSTATE.EL == EL2 then
    X[t, 64] = ISR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = ISR_EL1;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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